By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced attempt tools for SRAMs: potent recommendations for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics is dependent upon nanoscaled applied sciences that current new demanding situations when it comes to checking out and prognosis. stories are really liable to defects seeing that they take advantage of the know-how limits to get the top density. This ebook is a useful advisor to the checking out and prognosis of the newest new release of SRAM, some of the most general kind of stories. Classical tools for trying out reminiscence are designed to deal with the so-called "static faults", yet those attempt recommendations will not be enough for faults which are rising within the most recent Very Deep Sub-Micron (VDSM) applied sciences. those new faults, known as "dynamic faults", aren't coated by means of classical algorithms and require the committed attempt and prognosis strategies offered during this book.
- First e-book to provide whole, cutting-edge assurance of dynamic fault trying out for SRAM memories;
- Presents content material utilizing a "bottom-up" technique, from the examine of factors of malfunctions as much as the new release of clever attempt options;
- Includes case stories masking all reminiscence elements (core-cells, handle decoders, write drivers, experience amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in each one reminiscence part and the ensuing dynamic fault modeling.
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Extra info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
In conclusion, with the action of one RES, element M1 allows the sensitization of RDF and DRDF, induced by defects Df2 and Df3. 4 Analysis and Test of dDRF 37 Fig. 4 Analysis and Test of dDRF Some resistive-open defects, which are placed in the refreshment loop of the corecell, may cause Data Retention Faults (DRFs). There are different forms of DRF depending on the location of the defect and its resistance value. In particular, two sub-cases of dDRFs can be identified and their sensitization can be done by using the RES principle, as seen before for the dRDFs, and by emphasizing natural noise phenomena in SRAMs such as the ground bounce (Dilillo et al.
In Dilillo et al. (2004b) and Dilillo et al. (2005b), the authors show that a core-cell can undergo a stress equivalent to a read operation (Read Equivalent Stress, RES) when a read/write operation is performed on other core-cells of the same row (connected to the same word line) and that RESs are more effective to sensitize dRDFs than actual read operations. When a core-cell is selected for a read/write operation, the pre-charge circuit is turned off in its bit line. For the bit lines that are not involved in the operation, the pre-charge circuit is commonly left ON (Adams 2002).
For the second requirement, a dedicated source of noise can be introduced during the application of the algorithm. Another testing way is the application of the algorithm in conditions that maximize the natural sources of noise in SRAMs. Among the possible noise sources in SRAMs, the ground bounce can be considered (Senthinathan and Prince 1991, Ding and Mazumder 2003). The ground bounce is caused by large instant current, due to the switching of multiple devices, through parasitic inductance at the ground node.
Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies by Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel